Understanding Inputs for Physical Design in VLSI

 

Physical design in VLSI (Very Large Scale Integration) is a critical phase where a circuit's logical design (netlist) is converted into a physical layout. This layout is crucial for chip fabrication and must meet all design specifications, including timing, power, and area constraints. Here, we delve into the primary inputs required for physical design, accompanied by images to illustrate key concepts.

1. Netlist (.v)

Format: Verilog (.v)
Provided by: Synthesis Team

The netlist is a textual representation of the circuit's components (logic gates, combinational and sequential circuits) and their interconnections. It defines the logical connectivity and can include components like resistors, capacitors, and transistors.

Example Verilog Netlist:

verilog
module and_gate(y, a, b);
  input a, b;
  output y;
  AND2 U1 (.Y(y), .A(a), .B(b));
endmodule

2. Synopsys Design Constraints (SDC)

Format: .sdc (written in TCL)
Provided by: Synthesis Team

SDC files include timing constraints that help meet the design's timing requirements. They define clocks, input and output delays, maximum and minimum delays, transition constraints, and clock uncertainties.

Common Constraints:

  • Create clock definition
  • Input/output delay
  • Maximum transition
  • Maximum capacitance
  • False paths and multicycle paths

3. Timing Library/Logical Library (.lib)

Format: Liberty file (.lib)
Provided by: Vendors

This library contains timing, functionality, and power information for standard cells and macros. It includes cell delays, setup and hold times, and design rules like maximum transition and capacitance. Libraries are provided for various Process, Voltage, and Temperature (PVT) corners.

4. Physical Library (.lef)

Format: Layout Exchange Format (.lef)
Provided by: Vendors

The physical library provides physical information about standard cells, macros, and pads, including their geometry, routing obstructions, and pin locations.

5. Technology File (.techlef/.tf)

Format: .techlef or .tf
Provided by: Foundry

This file contains details about the manufacturing process, including the number of metal layers, design rules, and the physical and electrical characteristics of each layer.

6. TLU+ (Table Lookup)

Format: .tlup
Provided by: Foundry

The TLU+ file provides wire capacitance data for different net lengths and spacings, essential for calculating net delays accurately.

Sanity Checks Before Starting Physical Design

Before beginning the physical design flow, it's essential to ensure all input files are accurate and complete. These sanity checks help prevent issues during the design process.

1. Design/Netlist Checks:

  • Ensure no floating pins, multidriven nets, or unconstrained paths.
  • Identify and resolve undriven input ports and unloaded outputs.

2. SDC Checks:

  • Verify clock definitions and ensure clocks reach all flip-flop clock pins.
  • Check for unconstrained paths and endpoints.

3. Library Checks:

  • Validate consistency between logical and physical libraries.
  • Ensure all required cells and pins are correctly defined.

By conducting these checks and ensuring the accuracy of your inputs, you can streamline the physical design process and mitigate potential issues early on.

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