Floorplanning in Physical Design

  Floorplanning is a critical stage in the physical design of integrated circuits (ICs). It involves the strategic placement of various components on a chip to ensure optimal performance, minimal area, and efficient power distribution. A well-executed floorplan lays the foundation for a successful IC design, impacting factors such as routing complexity, signal integrity, and overall power consumption.


Essential Inputs for Floorplanning

Before diving into floorplanning, it's essential to gather and prepare the necessary inputs:

  1. Netlist (.v): The list of circuit elements and their connections.
  2. Technology File (techlef): Contains information about the technology node and design rules.
  3. Timing Library Files (.lib): Provides timing information for different cells.
  4. Physical Library (.lef): Details the physical dimensions and characteristics of cells.
  5. Synopsys Design Constraints (.sdc): Specifies the design constraints.
  6. Tlu+: Lookup tables for resistance and capacitance values used in delay calculations.

Steps in Floorplanning

  1. Decide Core Width and Height: Estimate the die size based on the design requirements.
  2. Create IO Pad Sites: Define locations for input/output pads.
  3. Place Macros: Strategically position large functional blocks (macros).
  4. Create Standard Cell Rows: Designate rows for placing standard cells.
  5. Power Planning: Develop a power distribution network, including pre-routing for power and ground.

Floorplan Control Parameters

  1. Aspect Ratio: The ratio of chip width to height, affecting the shape and size of the chip.
  2. Core Utilization: Defines the area occupied by standard cells, macros, and other elements. A typical core utilization of 80% indicates that 80% of the core area is used for component placement, leaving 20% for routing.

Guidelines for Macro Placement

  • Minimize Interconnect Length: Use fly lines (virtual connections) to reduce the distance between connected elements.
  • Place Near Core Boundary: Macros communicating with core pins should be near the core boundary to minimize routing complexity.
  • Avoid Notches: Ensure no notches in macro placement to avoid routing issues.
  • Maintain Sufficient Channel Width: Calculate channel width based on the number of pins and routing layers to prevent congestion.
  • Use Keep-out Margins: Define regions around macros where no other cells can be placed to avoid congestion and ensure better quality of results (QoR).

Types of Floorplanning Techniques

  1. Abutted Floorplanning: No gaps between blocks, leading to dense placement.
  2. Non-Abutted Floorplanning: Gaps between blocks, allowing for easier routing but potentially larger area.
  3. Mixed Approach: Combines both techniques for a balanced design.

Output of Floorplanning

  1. Core and Boundary Area: Defined and optimized.
  2. IO Ports/Pins Placement: Strategically placed to meet design requirements.
  3. Macro Placement: Optimally positioned for performance and area.
  4. Floorplan DEF File: Detailed description of the floorplan for further stages in the design process.



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