Sanity Checks

Sanity checks are a crucial step before beginning the physical design flow in VLSI. These checks ensure that the inputs received from the library team and the synthesis team are correct and free of errors. Neglecting these checks can lead to significant issues in the later stages of design. Let's explore the essential sanity checks performed before starting the physical design flow.

Design/Netlist Checks

These checks verify the quality and consistency of the netlist. Key aspects include:

  1. Floating Pins: Ensuring there are no pins in the design that are not connected to any net.
  2. Multidriven Nets: Checking for nets driven by multiple sources, which can lead to contention.
  3. Undriven Input Ports: Ensuring all input ports have driving sources.
  4. Unloaded Outputs: Verifying that all outputs have loads connected.
  5. Unconstrained Pins: Ensuring all pins have constraints defined.
  6. Pin Mismatch Counts: Checking for discrepancies between the pins of an instance and its reference.
  7. Tristate Buses with Non-Tristate Drivers: Ensuring that buses designed for tristate operation are not driven by non-tristate drivers.
  8. Wire Loops Across Hierarchies: Checking for loops that span across different hierarchical levels.

The ICC command used for these checks is check_design, which identifies issues such as multi-driven nets, floating nets/pins, and pin mismatches.

SDC Checks

These checks ensure that the design constraints specified in the Synopsys Design Constraints (SDC) file are correctly defined and adhered to. Key aspects include:

  1. Unconstrained Paths: Identifying paths in the design that lack constraints, as these will not be optimized by the PNR tool.
  2. Clock Reachability: Ensuring the clock signal reaches all clock pins of flip-flops.
  3. Multiple Clocks Driving Same Registers: Checking if any register is driven by multiple clocks.
  4. Unconstrained Endpoints: Verifying that all endpoints have timing constraints.
  5. Missing Port Delays: Ensuring all ports have input/output delay constraints.
  6. Missing Slew/Load Constraints: Verifying that slew and load constraints are defined for all ports.

The ICC command used for these checks is check_timing.

Library Checks

Library checks validate the consistency and quality of the logical and physical libraries. Key aspects include:

  1. Consistency Checks: Ensuring the logical library aligns with the physical library in terms of cell definitions and characteristics.
  2. Quality Checks: Verifying the quality of both the logical and physical libraries to ensure they meet the design requirements.

The command check_library is used to show the library name, type, version, and various metrics such as time units, capacitance, leakage power, and current. It also reports any missing cells or pins in the libraries.


Sanity checks are essential to ensure the reliability and accuracy of the inputs used in the physical design flow. By performing thorough design/netlist, SDC, and library checks, designers can mitigate issues early in the process, leading to a smoother and more efficient design phase. These checks not only help in identifying potential problems but also ensure that the design adheres to the specified constraints and quality standards. 

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